The invention relates to a memory component (CBRAM) having memory cells based on an active solid electrolyte material having a changeable resistance value and which, embedded between a bottom and top electrode, can be switched between an on state with a low resistance and an off state with a high resistance by comparison therewith by application of a suitable electric field between said electrodes, and to a fabrication method therefor.
Various semiconductor memory technologies based on the principle of switching the electrical resistance are currently being researched intensively. One promising concept based on a solid electrolyte material is also known in the literature as PMC (Programmable Metallization Cell) or CBRAM (Conductive Bridging Random Access Memory) (cf.: M. N. Kozicki, M. Yun, L. Hilt, A. Singh, Applications of programmable resistance changes in metal-doped chalcogenides, Electrochemical Society Proc., Vol. 99-13 (1999) 298; R. Neale, Micron to look again at non-volatile amorphous memory, Electron Engineering Design (2002); B. Prince, Emerging Memories—Technologies and Trends, Kluwer Academic Publishers (2002); R. Symanczyk et al. Electrical Characterization of Solid State Ionic Memory Elements, Proceedings Non-Volatile Memory Technology Symposium (2003) 17-1).
The functional principle makes use of the formation and the clearing of a low-resistance channel in a high-resistance solid electrolyte material upon application of suitable electrical fields. A resistive switching between the high-resistance state and a low-resistance state is thereby possible. The two resistance values can respectively be assigned a logic state.
Very high ratios of the off resistance to the on resistance are achieved in the case of the abovementioned CBRAM memory cells, due to the very high-resistance state of the solid electrolyte material in the non-programmed state. Typical values are R(off)/R(on)>106 given R(off)>1010Ω and an active cell area <1 μm2. At the same time, this technology is characterized by low switching voltages of less than 100 mV for initiating the erase operation and less than 300 mV for the write operation.
When realizing a cell array with evaluation and drive logic, however, the high resistance values are associated with a number of disadvantages:                sensitivity toward interference voltages;        large feedback resistance in a typical sense amplifier and thus a high area requirement in the case of embodiment in CMOS technology; and        high RC time constants.        
The interference susceptibility of a cell with extremely high R(off) is particularly critical. Since even the resistance of a switched-off field effect transistor is in the region of 1010Ω, a circuit node between such a transistor and a high-resistance CBRAM memory cell is practically completely isolated and thus very sensitive toward instances of capacitive coupling in. Moreover, even extremely low leakage currents lead to the build-up of interference voltages. Both effects may result in an undesirable programming of the CBRAM cell.
Furthermore, the cells exhibit degradation of the off state over the service life, particularly under stress conditions such as endurance tests. This degradation is manifested in a reduction of the off resistance and means an undesirable inhomogeneity of the cell characteristic values in a memory array and over the operation period of the component.
Further memory concepts exist which are based on memory cells that can be switched in terms of their resistance value, such as, for example, MRAM or PCRAM memories. In the case of these concepts, the off/on resistance ratio and also the switch-off resistance are significantly lower in comparison with a CBRAM. The problem area described here does not occur in this form in these other memory concepts. Off/on resistance ratios of up to 70% are achieved in an MRAM, and in a PCRAM the values are typically in the region of less than 103 with an R(off) of less than 1 MΩ.